Conventional semiconductor devices typically comprise a semiconductor substrate, normally made of monocrystalline silicon, and a plurality of dielectric and conductive layers formed thereon. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Such interconnection lines generally constitute a limiting factor in terms of various functional characteristics of the integrated circuit. There exists a need to provide a reliable interconnection structure capable of achieving higher operating speeds, improved signal-to-noise ratio, improved wear characteristics and improved reliability.
Most interconnection lines are made of aluminum or an aluminum-base alloy. The performance of a semiconductor device could be improved by forming the interconnection line of a metal having a higher conductivity than aluminum, thereby increasing current handling capability. It is known that copper, copper-base alloys, gold, gold-base alloys, silver and silver-base alloys generally exhibit a higher conductivity than aluminum and aluminum-base alloys. However, those having ordinary skill in the art have shunned the use of copper for forming an interconnection line, because copper readily diffuses through silicon dioxide, the typical dielectric material employed in the manufacture of semiconductor devices, and adversely affects active silicon devices. Moreover, a low cost satisfactory method for joining a bonding pad to copper for external connection has yet to be developed.
According to conventional practices, a plurality of conductive layers are formed above a semiconductor substrate, and the uppermost conductive layer joined to a bonding pad for forming an external electrical connection. The uppermost conductive layer which is connected externally is typically referred to as the wire bonding layer. A "scratch protection" (topside) dielectric layer is normally formed on the wire bonding layer, to prevent contamination of the semiconductor device during assembly and provide resistance to moisture, sodium, etc.
In the conventional semiconductor device illustrated in FIG. 1, p-type semiconductor substrate 1 is provided with field oxide 2 for isolating an active region comprising N+ source/drain regions 3, and a gate electrode 4, typically of polysilicon, above the semiconductor substrate with gate oxide 5 therebetween. Interlayer dielectric layer 6, typically silicon dioxide, is then deposited thereover and openings formed by conventional photolithographic and etching techniques for establishing electrical contact between subsequently deposited conductive layer 8, typically of aluminum or an aluminum-base alloy, and source/drain regions 3 through vias 7, and to transistor gate 4a. Dielectric layer 9, typically silicon dioxide, is deposited on conductive layer 8, and another conductive layer 10, typically aluminum or an aluminum-base alloy, formed on dielectric layer 9 and electrically connected to conductive layer 8 through vias 11.
With continued reference to FIG. 1, conductive layer 10 is the uppermost conductive layer and, hence, constitutes the wire bonding layer. Dielectric layer 12, also typically silicon dioxide, is deposited, and a protective dielectric scratch resistant ("topcoat") layer 13 deposited thereon. Protective dielectric layer 13 typically comprises silicon nitride (Si.sub.3 N.sub.4) or a silicon oxynitride (SiOxNy), and basically provides scratch protection to the semiconductor device and protection against moisture and impurity contamination during subsequent processing. After deposition of the protective dielectric layer 13, conventional photolithographic and etching techniques are employed to form an opening to expose wire bonding layer 10 for external connection by means of bonding pad 14 and electrically conductive wires 15 or an external connection electrode (not shown).
Although only two conductive layers 8 and 10 are illustrated in FIG. 1 for simplicity, conventional semiconductor devices are not so limited and may comprise more than two conductive layers, depending on design requirements. Also in the interest of simplicity, FIG. 1 does not illustrate any particular type of plug or barrier layer technology. However, such technology is conventional and, therefore, the details of such features are not set forth herein.
The escalating requirements of current carrying capacity, higher operating speeds, improved reliability, wear characteristics, signal-to-noise ratios, and miniaturization, require corresponding improvements in the materials and design of conventional semiconductor devices, such as that depicted in FIG. 1.